In recent years, the main memory widely used in personal computers, and the like, has been synchronous memory which performed operations synchronized with clock signals. In particular, double data rate (DDR) synchronous memory requires that input/output data be accurately synchronized with external clock signals, and thus requires a delay locked loop (DLL) circuit to generate internal clock signals that are synchronized with external clock signals.
In one example, Patent Document 1 describes dynamic random access memory (DRAM) including a DLL circuit. The DRAM described in Patent Document 1 controls the output of data read from memory cells and the self-refresh timing of memory cells, etc., on the basis of internal clock signals generated by the DLL circuit.
Patent Document 2 describes a DLL circuit used in a semiconductor memory device. The DLL circuit described in Patent Document 2 has a coarse delay line (CDL) with a coarsely adjusted pitch and a fine delay line (FDL) with a finely adjusted pitch. After the amount of delay has been roughly set using the coarse delay line (CDL), the amount of delay is set more accurately using the fine delay line (FDL). In this way, the amount of delay can be determined very quickly.
Patent Document 3 describes a DLL circuit comprising a clock generating circuit for dividing external clock signals and generating operating clock signals based on the divided clock signals, a counter circuit synchronized with the generated operating clock signals for updating a count value, and a delay line for delaying the external clock signals on the basis of the amount of delay determined by the count value and generating internal clock signals.
Patent Document 4 describes a DLL circuit comprising a variable delay circuit for generating internal clock signals by delaying external clock signals, and a dividing circuit for dividing the external clock signals to generate sampling clock signals, the resulting sampling clock signals being used as synchronization signals indicating the timing on which the amount of delay is changed by the variable delay circuit.